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6-channel, low noise, low power, 24-/16-bit - adc with on-chip in-amp and reference ad7794/ad7795 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2007 analog devices, inc. all rights reserved. features up to 23 effective bits rms noise: 40 nv @ 4.17 hz, 85 nv @ 16.7 hz current: 400 a typical power-down: 1 a maximum low noise, programmable gain, instrumentation amp band gap reference with 4 ppm/c drift typical update rate: 4.17 hz to 470 hz six differential analog inputs internal clock oscillator simultaneous 50 hz/60 hz rejection reference detect programmable current sources on-chip bias voltage generator burnout currents low-side power switch power supply: 2.7 v to 5.25 v temperature range: b grade: C40c to +105c c grade: C40c to +125c independent interface power supply 24-lead tssop 3-wire serial interface spi?, qspi?, microwire?, and dsp compatible schmitt trigger on sclk applications temperature measurement pressure measurement weigh scales strain gage transducers gas analysis industrial process control instrumentation blood analysis smart transmitters liquid/gas chromatography 6-digit dvm general description the ad7794/ad7795 are low power, low noise, complete analog front ends for high precision measurement applications. they contain a low noise, 24-/16-bit - adc with six differential inputs. the on-chip low noise instrumentation amplifier means that signals of small amplitude can be interfaced directly to the adc. each device contains a precision, low noise, low drift internal band gap reference, and can also accept up to two external differential references. other on-chip features include programmable excitation current sources, burnout currents, and a bias voltage generator that is used to set the common- mode voltage of a channel to av dd /2. the low-side power switch can be used to power down bridge sensors between conversions, minimizing the systems power consumption. the ad7794/ad7795 can operate with either an internal clock or an external clock. the output data rate from each part can vary from 4.17 hz to 470 hz. both parts operate with a power supply from 2.7 v to 5.25 v. the b-grade parts (ad7794 and ad7795) are specified for a temperature range of ?40c to +105c while the c-grade part (ad7794) is specified for a temperature range of ?40c to +125c. they consume a current of 400 a typical and are housed in a 24-lead tssop. functional block diagram 04854-001 dout/rd y din sclk cs dv dd serial interface and logic control - adc ad7794: 24-bit adc ad7795: 16-bit adc ad7794/ad7795 ain1(+) ain1(?) ain2(+) ain2(?) ain3(+) ain3(?) a in5(+)/iout2 a in5(?)/iout1 ain6(+)/p1 ain6(?)/p2 v dd gnd mux v bias psw gnd band gap reference temp sensor clk internal clock gnd reference detect gnd a v dd a in4(+) / refin2(+) refin1(+) a in4( ? ) / refin2( ? ) refin1( ? ) v dd in-amp buf figure 1.
ad7794/ad7795 rev. d | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ..................................................................... 8 timing diagrams .............................................................................. 9 absolute maximum ratings .......................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 rms noise and resolution specifications .................................. 13 chop enabled .............................................................................. 13 chop disabled ............................................................................ 15 typical performance characteristics ........................................... 16 on-chip registers .......................................................................... 17 communications register ......................................................... 17 status register ............................................................................. 18 mode register ............................................................................. 19 configuration register .............................................................. 22 data register ............................................................................... 24 id register ................................................................................... 24 io register ................................................................................... 24 offset register ............................................................................. 25 full-scale register ...................................................................... 25 adc circuit information .............................................................. 26 overview ..................................................................................... 26 digital interface .......................................................................... 28 circuit description ......................................................................... 31 analog input channel ............................................................... 31 instrumentation amplifier ........................................................ 31 bipolar/unipolar configuration .............................................. 31 data output coding .................................................................. 32 burnout currents ....................................................................... 32 excitation currents .................................................................... 32 bias voltage generator .............................................................. 32 reference ..................................................................................... 32 reference detect ......................................................................... 33 reset ............................................................................................. 33 av dd monitor ............................................................................. 33 calibration ................................................................................... 33 grounding and layout .............................................................. 34 applications information .............................................................. 35 flowmeter .................................................................................... 35 outline dimensions ....................................................................... 36 ordering guide .......................................................................... 36 revision history 3/07rev. c to rev. d changes to specifications endnote 1............................................. 7 changes to status register section .............................................. 18 changes to ordering guide .......................................................... 36 10/06rev. b to rev. c updated format..................................................................universal added ad7794 c-grade part...........................................universal changes to specifications ................................................................ 3 changes to ordering guide .......................................................... 36 6/06rev. a to rev. b added ad7795 ...................................................................universal changes to features.......................................................................... 1 changes to table 1............................................................................ 3 changes to rms noise and resolution specifications section..................................................................... 12 changes to table 19........................................................................ 20 changes to adc circuit information section ........................... 25 changes to ordering guide .......................................................... 35 4/05rev. 0 to rev. a changes to absolute maximum ratings........................................9 changes to figure 21...................................................................... 25 changes to data output coding section.................................... 28 changes to calibration section .................................................... 30 changes to ordering guide .......................................................... 33 10/04revision 0: initial version
ad7794/ad7795 rev. d | page 3 of 36 specifications av dd = 2.7 v to 5.25 v, dv dd = 2.7 v to 5.25 v, gnd = 0 v, all specifications t min to t max , unless otherwise noted. table 1. parameter 1 ad7794/ad7795 unit test conditions/comments chop enabled output update rate 4.17 to 470 hz nom settling time = 2/output update rate no missing codes 2 ad7794 24 bits min f adc 242 hz ad7795 16 bits min resolution see the rms noise and resolution specifications section rms noise and update rates see the rms noise and resolution specifications section integral nonlinearity 15 ppm of fsr max offset error 3 1 v typ offset error drift vs. temperature 4 10 nv/c typ full-scale error 3 , 5 10 v typ gain drift vs. temperature 4 1 ppm/c typ gain = 1 to 16, external reference 3 ppm/c typ gain = 32 to 128, external reference power supply rejection 100 db min ain = 1 v/gain, gain 4, external reference analog inputs differential input voltage ranges vref/gain v nom v ref = refin(+) ? refin(?), or internal reference, gain = 1 to 128 absolute ain voltage limits 2 unbuffered mode gnd ? 30 mv v min gain = 1 or 2 av dd + 30 mv v max buffered mode gnd + 100 mv v min gain = 1 or 2 av dd ? 100 mv v max in-amp active gnd + 300 mv v min gain = 4 to 128 av dd ? 1.1 v max common-mode voltage, v cm 0.5 v min vcm = (ain(+) + ain(?))/2, gain = 4 to 128 analog input current buffered mode or in-amp active average input current 2 ad7794b/ad7795b 1 na max gain = 1 or 2, update rate < 100 hz 250 pa max gain = 4 to 128, update rate < 100 hz 1 na max ain6(+)/ain6(?) ad7794c 3 na max gain = 1 or 2, update rate < 100 hz 2 na max gain = 4 to 128, update rate < 100 hz 3 na max ain6(+)/ain6(?) average input current drift 2 pa/c typ unbuffered mode gain = 1 or 2 average input current 400 na/v typ input current varies with input voltage average input current drift 50 pa/v/c typ normal mode rejection 2 , 6 internal clock @ 50 hz, 60 hz 65 db min 80 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz 80 db min 90 db typ, 50 1 hz, fs[3:0] = 1001 @ 60 hz 90 db min 100 db typ, 60 1 hz, fs[3:0] = 1000 external clock @ 50 hz, 60 hz 80 db min 90 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz 94 db min 100 db typ, 50 1 hz, fs[3:0] = 1001 @ 60 hz 90 db min 100 db typ, 60 1 hz, fs[3:0] = 1000
ad7794/ad7795 rev. d | page 4 of 36 parameter 1 ad7794/ad7795 unit test conditions/comments common-mode rejection ad7794b/ad7795b @ dc 100 db min ain = 1 v/gain, gain 4 @ 50 hz, 60 hz 2 100 db min 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz, 60 hz 2 100 db min 50 1 hz, fs[3:0] = 1001; 60 1 hz, fs[3:0] = 1000 ad7794c @ dc 97 db min ain = 1 v/gain, gain 4 @ 50 hz, 60 hz 2 97 db min 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz, 60 hz 2 97 db min 50 1 hz, fs[3:0] = 1001; 60 1 hz, fs[3:0] = 1000 chop disabled output update rate 4.17 to 470 hz nom settling time = 1/output update rate no missing codes 2 ad7794 24 bits min f adc 123 hz ad7795 16 bits min resolution see the rms noise and resolution specifications section rms noise and update rates see the rms noise and resolution specifications section integral nonlinearity 15 ppm of fsr max offset error 3 100/gain v typ without calibration offset error drift vs. temperature 4 100/gain nv/c typ gain = 1 to 16 10 nv/c typ gain = 32 to 128 full-scale error 3 , 5 10 v typ gain drift vs. temperature 4 1 ppm/c typ gain = 1 to 16, external reference 3 ppm/c typ gain = 32 to 128, external reference power supply rejection 100 db typ ain = 1 v/gain, gain 4, external reference analog inputs differential input voltage ranges v ref /gain v nom v ref = refin(+) ? refin(?), or internal reference, gain = 1 to 128 absolute ain voltage limits 2 unbuffered mode gnd ? 30 mv v min gain = 1 or 2 av dd + 30 mv v max buffered mode gnd + 100 mv v min gain = 1 or 2 av dd ? 100 mv v max in-amp active gnd + 300 mv v min gain = 4 to 128 av dd ? 1.1 v max common-mode voltage, v cm 0.2 + (gain/2 (ain(+) ? ain(?))) v min amp ? cm = 1, vcm = (ain(+) + ain(C))/2, gain = 4 to 128 av dd ? 0.2 ? (gain/2 (ain(+) ? ain(?))) v max analog input current buffered mode or in-amp active average input current 2 ad7794b/ad7795b 1 na max gain = 1 or 2 250 pa max gain = 4 to 128 1 na max ain6(+)/ain6(?) ad7794c 3 na max gain = 1 or 2 2 na max gain = 4 to 128 3 na max ain6(+)/ain6(?) average input current drift 2 pa/c typ unbuffered mode gain = 1 or 2 average input current 400 na/v typ input current varies with input voltage average input current drift 50 pa/v/c typ
ad7794/ad7795 rev. d | page 5 of 36 parameter 1 ad7794/ad7795 unit test conditions/comments normal mode rejection 2 , 6 internal clock @ 50 hz, 60 hz 60 db min 70 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz 78 db min 90 db typ, 50 1 hz, fs[3:0] = 1001 @ 60 hz 86 db min 100 db typ, 60 1 hz, fs[3:0] = 1000 external clock @ 50 hz, 60 hz 60 db min 70 db typ, 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz 94 db min 100 db typ, 50 1 hz, fs[3:0] = 1001 @ 60 hz 90 db min 100 db typ, 60 1 hz, fs[3:0] = 1000 common-mode rejection ad7794b/ad7795b @ dc 100 db min ain = 1 v/gain, with gain = 4, amp-cm bit = 1 @ 50 hz, 60 hz 2 100 db min 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz, 60 hz 2 100 db min 50 1 hz, fs[3:0] = 1001; 60 1 hz, fs[3:0] = 1000 ad7794c @ dc 97 db min ain = 1 v/gain, with gain = 4, amp-cm bit = 1 @ 50 hz, 60 hz 2 97 db min 50 1 hz, 60 1 hz, fs[3:0] = 1010 @ 50 hz, 60 hz 2 97 db min 50 1 hz, fs[3:0] = 1001; 60 1 hz, fs[3:0] = 1000 chop enabled or disabled reference input internal reference internal reference initial accuracy 1.17 0.01% v min/max av dd = 4 v, t a = 25c internal reference drift 2 4 ppm/c typ 15 ppm/c max power supply rejection 85 db typ external reference external refin voltage 2.5 v nom refin = refin(+) ? refin(?) reference voltage range 2 0.1 v min av dd v max when v ref = av dd , the differential input must be limited to 0.9 v ref /gain if the in-amp is active absolute refin voltage limits 2 gnd ? 30 mv v min av dd + 30 mv v max average reference input current 400 na/v typ average reference input current drift 0.03 na/v/c typ normal mode rejection 2 same as for analog inputs common-mode rejection 100 db typ reference detect levels 0.3 v min 0.65 v max noxref bit active if v ref < 0.3 v excitation current sources (iexc1 and iexc2) output current 10/210/1000 a nom initial tolerance at 25c 5 % typ drift 200 ppm/c typ current matching 0.5 % typ matching between iexc1 and iexc2, v out = 0 v drift matching 50 ppm/c typ line regulation (av dd ) 2 %/v typ av dd = 5 v 5% load regulation 0.2 %/v typ output compliance av dd ? 0.65 v max current sources programmed to 10 a or 210 a av dd ? 1.1 v max current sources programmed to 1 ma gnd ? 30 mv v min
ad7794/ad7795 rev. d | page 6 of 36 parameter 1 ad7794/ad7795 unit test conditions/comments bias voltage generator v bias av dd /2 v nom v bias generator start-up time ms/nf typ dependent on the capacitance connected to ain; see figure 11 temperature sensor accuracy 2 c typ applies if user calibrates the temperature sensor sensitivity 0.81 mv/c typ low-side power switch r on 7 max av dd = 5 v 9 max av dd = 3 v allowable current 2 30 ma max continuous current digital outputs (p1 and p2) v oh , output high voltage 2 av dd ? 0.6 v min av dd = 3 v, i source = 100 a v ol , output low voltage 2 0.4 v max av dd = 3 v, i sink = 100 a v oh , output high voltage 2 4 v min av dd = 5 v, i source = 200 a v ol , output low voltage 2 0.4 v max av dd = 5 v, i sink = 800 a internal/external clock internal clock frequency 2 64 3% khz min/max duty cycle 50:50 % typ external clock frequency 64 khz nom a 128 khz external clock can be used if the divide-by-2 function is used (bit clk1 = clk0 = 1) duty cycle 45:55 to 55:45 % typ applies for external 64 khz clock, a 128 khz clock can have a less stringent duty cycle logic inputs cs 2 v inl , input low voltage 0.8 v max dv dd = 5 v 0.4 v max dv dd = 3 v v inh , input high voltage 2.0 v min dv dd = 3 v or 5 v sclk (schmitt-triggered input), clk, and din 2 ad7794b/ad7795b v t (+) 1.4/2 v min/max dv dd = 5 v v t (?) 0.8/1.7 v min/max dv dd = 5 v v t (+) to v t (?) 0.1/0.17 v min/max dv dd = 5 v v t (+) 0.9/2 v min/max dv dd = 3 v v t (?) 0.4/1.35 v min/max dv dd = 3 v v t (+) to v t (?) 0.06/0.13 v min/max dv dd = 3 v ad7794c v t (+) 1.35/2.05 v min/max dv dd = 5 v v t (?) 0.8/1.9 v min/max dv dd = 5 v v t (+) to v t (?) 0.1/0.19 v min/max dv dd = 5 v v t (+) 0.9/2 v min/max dv dd = 3 v v t (?) 0.4/1.35 v min/max dv dd = 3 v v t (+) to v t (?) 0.06/0.15 v min/max dv dd = 3 v input currents 10 a max v in = dv dd or gnd input capacitance 10 pf typ all digital inputs
ad7794/ad7795 rev. d | page 7 of 36 parameter 1 ad7794/ad7795 unit test conditions/comments logic output (including clk) v oh , output high voltage 2 dv dd ? 0.6 v min dv dd = 3 v, i source = 100 a v ol , output low voltage 2 0.4 v max dv dd = 3 v, i sink = 100 a v oh , output high voltage 2 4 v min dv dd = 5 v, i source = 200 a v ol , output low voltage 2 0.4 v max dv dd = 5 v, i sink = 1.6 ma (dout/ rdy ), 800 a (clk) floating-state leakage current 10 a max floating-state output capacitance 10 pf typ data output coding offset binary system calibration 2 full-scale calibration limit 1.05 fs v max zero-scale calibration limit ?1.05 fs v min input span 0.8 fs v min 2.1 fs v max power requirements 7 power supply voltage av dd to gnd 2.7/5.25 v min/max dv dd to gnd 2.7/5.25 v min/max power supply currents i dd current 140 a max 110 a typ @ av dd = 3 v, 125 a typ @ av dd = 5 v, unbuffered mode, external reference 185 a max 130 a typ @ av dd = 3 v, 165 a typ @ av dd = 5 v, buffered mode, gain = 1 or 2, external reference 400 a max 300 a typ @ av dd = 3 v, 350 a typ @ av dd = 5 v, gain = 4 to 128, external reference 500 a max 400 a typ @ av dd = 3 v, 450 a typ @ av dd = 5 v, gain = 4 to 128, internal reference i dd (power-down mode) 1 a max ad7794b, ad7795b 2 a max ad7794c 1 temperature range: b grade: ?40 c to +105c, c grade: ? 40c to +125c. at the 19.6 hz and 39.2 hz update rates, the inl, power supply rejection (psr), common- mode rejection (cmr), and normal mode rejection (nmr) do not meet the data sheet specification if the voltage on the ain(+) or ain(?) pins exceeds av dd C 1.6 v typically. in addition, the offset error and offset error drift degrade at these update rates when chopping is disabled. when t his voltage is exceeded, the inl, for example, is reduced to 18 ppm of fs typically while the psr is reduced to 69 db typically. therefore, for guaranteed performanc e at these update rates, the absolute voltage on the analog input pins needs to be below avdd ? 1.6 v. 2 specification is not production tested but is supported by characterization data at initial product release. 3 following a calibration, this error is in the order of the noise for the programmed gain an d update rate selected. 4 recalibration at any temper ature removes these errors. 5 full-scale error applies to both positive and negative full -scale, and applies at the fact ory calibration conditions (av dd = 4 v, gain = 1, t a = 25c). 6 fs[3:0] are the four bits used in the mode register to select the output word rate. 7 digital inputs equal to dv dd or gnd with excitation currents an d bias voltage generator disabled.
ad7794/ad7795 rev. d | page 8 of 36 timing characteristics av dd = 2.7 v to 5.25 v, dv dd = 2.7 v to 5.25 v, gnd = 0 v, input logic 0 = 0 v, input logic 1 = dv dd , unless otherwise noted. table 2. parameter 1 , 2 limit at t min , t max (b version) unit conditions/comments t 3 100 ns min sclk high pulse width t 4 100 ns min sclk low pulse width read operation t 1 0 ns min cs falling edge to dout/ rdy active time 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 2 3 0 ns min sclk active edge to data valid delay 4 60 ns max dv dd = 4.75 v to 5.25 v 80 ns max dv dd = 2.7 v to 3.6 v t 5 5 , 6 10 ns min bus relinquish time after cs inactive edge 80 ns max t 6 0 ns min sclk inactive edge to cs inactive edge t 7 10 ns min sclk inactive edge to dout/ rdy high write operation t 8 0 ns min cs falling edge to sclk active edge setup time 4 t 9 30 ns min data valid to sclk edge setup time t 10 25 ns min data valid to sclk edge hold time t 11 0 ns min cs rising edge to sclk edge hold time 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.6 v. 2 see figure 3 and figure 4. 3 these numbers are measured with the load ci rcuit shown in figure 2 and defined as the time required for the output to cross th e v ol or v oh limits. 4 sclk active edge is falling edge of sclk. 5 these numbers are derived from the measured time taken by the data output to change 0.5 v when loaded with the circuit shown i n figure 2. the measured number is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the times quote d in the timing characteristics are the true bus relinquish times of the part and, therefore, are independent of external bus loading capacitances. 6 rdy returns high after a read of the adc. in single conversion mode and continuous conversion mode, the same data can be read agai n, if required, while rdy is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. in continuous read mode, the digital word can be read only once. 04854-002 i sink (1.6ma with dv dd =5v, 100a with dv dd =3v) i source (200a with dv dd =5v, 100a with dv dd =3v) 1.6v to output pin 50pf figure 2. load circuit for timing characterization
ad7794/ad7795 rev. d | page 9 of 36 timing diagrams 0 4854-003 t 2 t 3 t 4 t 1 t 6 t 5 t 7 cs (i) dout/rdy (o) sclk (i) i= input, o= output msb lsb figure 3. read cycle timing diagram 0 4854-004 i = input, o = output cs (i) sclk (i) din (i) msb lsb t 8 t 9 t 10 t 11 figure 4. write cycle timing diagram
ad7794/ad7795 rev. d | page 10 of 36 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd ?0.3 v to +7 v dv dd to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to av dd + 0.3 v reference input voltage to gnd ?0.3 v to av dd + 0.3 v digital input voltage to gnd ?0.3 v to dv dd + 0.3 v digital output voltage to gnd ?0.3 v to dv dd + 0.3 v ain/digital input current 10 ma operating temperature range b grade ?40c to +105c c grade ?40c to +125c storage temperature range ?65c to +150c maximum junction temperature 150c tssop ja thermal impedance 97.9c/w jc thermal impedance 14c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7794/ad7795 rev. d | page 11 of 36 pin configuration and fu nction descriptions 0 4854-005 nc = no connect ad7794/ ad7795 top view (not to scale) sclk 1 din 24 clk 2 dout/rdy 23 cs 3 dv dd 22 nc 4 av dd 21 a in6(+)/p1 5 gnd 20 a in6(?)/p2 6 psw 19 ain1(+) 7 ain4(?)/refin2(?) 18 ain1(?) 8 ain4(+)/refin2(+) 17 ain2(+) 9 ain5(?)/iout1 16 ain2(?) 10 ain5(+)/iout2 15 ain3(+) 11 refin1(?) 14 ain3(?) 12 refin1(+) 13 figure 5. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 sclk serial clock input. this serial cloc k input is for data transfers to and from the adc. the sclk has a schmitt- triggered input, making the interface suitable for opto-isolated applications. the serial clock can be continuous with all data transmitted in a continuous train of pulses. alternatively, it can be a noncontinuous clock with the information being transmitted to or from the adc in smaller batches of data. 2 clk clock in/clock out. the internal clock can be made available at this pin. alternatively, the internal clock can be disabled, and the adc can be driven by an external clock. this allows several ad cs to be driven from a common clock, allowing simultaneous conversions to be performed. 3 cs chip select input. this is an active low logic input used to select the adc. cs can be used to select the adc in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. cs can be hardwired low, allowing the adc to operate in 3-wire mode with sclk, din, and dout used to interface with the device. 4 nc no connect. 5 ain6(+)/p1 analog input/digital output pin. ain6(+) is the posit ive terminal of the differ ential analog input pair, ain6(+)/ain6(?). this pin can al so function as a general-purpos e output bit referenced between av dd and gnd. 6 ain6(?)/p2 analog input/digital output pin. ain6(?) is the negati ve terminal of the differ ential analog input pair, ain6(+)/ain6(?). this pin can al so function as a general-purpos e output bit referenced between av dd and gnd. 7 ain1(+) analog input. ain1(+) is the positive terminal of the differential analog input pair, ain1(+)/ain1(?). 8 ain1(?) analog input. ain1(?) is the negative terminal of the differenti al analog input pair, ain1(+)/ain1(?). 9 ain2(+) analog input. ain2(+) is the positive terminal of the differential analog input pair, ain2(+)/ain2(?). 10 ain2(?) analog input. ain2(?) is th e negative terminal of the differential analog input pair, ain2(+)/ain2(?). 11 ain3(+) analog input. ain3(+) is the positive terminal of the differential analog input pair, ain3(+)/ain3(?). 12 ain3(?) analog input. ain3(?) is th e negative terminal of the differential analog input pair, ain3(+)/ain3(?). 13 refin1(+) positive reference input. an external reference can be applied between refin1(+) and refin1(?). refin1(+) can lie anywhere between av dd and gnd + 0.1 v. the nominal reference voltage, (refin1(+) ? refin1(?)), is 2.5 v, but the part functions with a reference from 0.1 v to av dd . 14 refin1(?) negative reference input. this reference input can lie anywhere between gnd and av dd ? 0.1 v. 15 ain5(+)/iout2 analog input/output of internal excita tion current source. ain5(+) is the positive terminal of the differential analog input pair ain5(+)/ain5 (?). alternatively, the intern al excitation current source can be made available at this pin and is programmable so that the current can be 10 a, 210 a, or 1 ma. either iexc1 or iexc2 can be switched to this output. 16 ain5(?)/iout1 analog input/output of internal ex citation current source. ain5(?) is the negative terminal of the differential analog input pair, ain5(+)/ain5(?). alternat ively, the internal excitati on current source can be made available at this pin and is programmable so th at the current can be 10 a, 210 a, or 1 ma. either iexc1 or iexc2 can be switched to this output. 17 ain4(+)/refin2(+) analog input/positive reference input. ain4(+) is the pos itive terminal of the differential analog input pair ain4(+)/ain4(?). this pin also functions as a positive reference input for refin2. refin2(+) can lie anywhere between av dd and gnd + 0.1 v. the nominal reference voltage (refin2(+) to refin2(?)) is 2.5 v, but the part functions with a reference from 0.1 v to av dd .
ad7794/ad7795 rev. d | page 12 of 36 pin no. mnemonic description 18 ain4(?)/refin2(?) analog input/negative reference input. ain4(?) is the negative terminal of the differential analog input pair ain4(+)/ain4(?). this pin also functi ons as the negative reference input for refin2. this reference input can lie anywhere between gnd and av dd ? 0.1 v. 19 psw low-side power switch to gnd. 20 gnd ground reference point. 21 av dd supply voltage, 2.7 v to 5.25 v. 22 dv dd serial interface supply voltage, 2.7 v to 5.25 v. dv dd is independent of av dd . therefore, the serial interface operates at 3 v with av dd at 5 v or vice versa. 23 dout/ rdy serial data output/data ready output. dout/ rdy serves a dual purpose. it functions as a serial data output pin to access the output shift register of the adc. the o utput shift register can contain data from any of the on-chip data or control registers. in addition, dout/ rdy operates as a data ready pin, going low to indicate the completion of a conversion. if the data is not re ad after the conversion, the pin goes high before the next update occurs. the dout/ rdy falling edge can also be used as an interrupt to a processor, indicating that valid data is available. with an external se rial clock, the data can be read using the dout/ rdy pin. with cs low, the data/control word info rmation is placed on the dout/ rdy pin on the sclk falling edge and is valid on the sclk rising edge. 24 din serial data input to the input shift register on the adc. data in this shift register is transferred to the control registers within the adc with the register selection bits of the communications register identifying the appropriate register.
ad7794/ad7795 rev. d | page 13 of 36 rms noise and resolution specifications the ad7794/ad7795 can be operated with chop enabled or chop disabled, allowing the adc to be optimized for switching time or drift performance. with chop enabled, the settling time is two times the conversion time. however, the offset is continuously removed by the adc leading to low offset and low offset drift. with chop disabled, the allowable update rates are the same as in chop enable mode. however, the settling time now equals the conversion time. with chop disabled, the offset is not removed by the adc, so periodic offset calibrations can be required to remove offset due to drift. chop enabled external reference table 5 shows the ad7794/ad7795 rms noise for some update rates and gain settings. the numbers given are for the bipolar input range with an external 2.5 v reference. these numbers are typical and are generated with a differential input voltage of 0 v. table 6 and table 7 show the effective resolution, while the output peak-to-peak (p-p) resolution is listed in brackets. it is important to note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. the p-p resolution represents the resolution for which there is no code flicker. these numbers are typical and are rounded to the nearest lsb. table 5. rms noise (v) vs. gain and output update rate using an external 2.5 v reference with chop enabled update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 0.64 0.6 0.29 0.22 0.1 0.065 0.039 0.041 8.33 1.04 0.96 0.38 0.26 0.13 0.078 0.057 0.055 16.7 1.55 1.45 0.54 0.36 0.18 0.11 0.087 0.086 33.2 2.3 2.13 0.74 0.5 0.23 0.17 0.124 0.118 62 2.95 2.85 0.92 0.58 0.29 0.2 0.153 0.144 123 4.89 4.74 1.49 1 0.48 0.32 0.265 0.283 242 11.76 9.5 4.02 1.96 0.88 0.45 0.379 0.397 470 11.33 9.44 3.07 1.79 0.99 0.63 0.568 0.593 table 6. effective resolution (bits) vs. gain and ou tput update rate for the ad7794 using an ex ternal 2.5 v reference with chop enabled update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 23 (20.5) 22 (19.5) 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 20 (17.5) 8.33 22 (19.5) 21.5 (19) 21.5 (19) 21 (18.5) 21 (18.5) 21 (18.5) 20.5 (18) 19.5 (17) 16.7 21.5 (19) 20.5 (18) 21 (18.5) 20.5 (18) 20.5 (18) 20.5 (18) 20 (17.5) 19 (16.5) 33.2 21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 20.5 (18) 20 (17.5) 19 (16.5) 18.5 (16) 62 20.5 (18) 19.5 (17) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 19 (16.5) 18 (15.5) 123 20 (17.5) 19 (16.5) 19.5 (17) 19 (16.5) 19.5 (17) 19 (16.5) 18 (15.5) 17 (14.5) 242 18.5 (16) 18 (15.5) 18 (15.5) 18 (15.5) 18.5 (16) 18.5 (16) 17.5 (15) 16.5 (14) 470 18.5 (16) 18 (15.5) 18.5 (16) 18.5 (16) 18 (15.5) 18 (15.5) 17 (14.5) 16 (13.5) table 7. effective resolution (bits) vs. gain and ou tput update rate for the ad7795 using an ex ternal 2.5 v reference with chop enabled update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 62 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 123 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 242 16 (16) 16 (15.5) 16 (15.5) 16 (15. 5) 16 (16) 16 (16) 16 (15) 16 (14) 470 16 (16) 16 (15.5) 16 (16) 16 (16) 16 (15.5) 16 (15.5) 16 (14.5) 16 (13.5)
ad7794/ad7795 rev. d | page 14 of 36 internal reference table 8 shows the ad7794/ad7795 rms noise for some of the update rates and gain settings. the numbers given are for the bipolar input range with the internal 1.17 v reference. these numbers are typical and are generated with a differential input voltage of 0 v. table 9 and table 10 show the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. it is important to note that the effective resolution is calculated using the rms noise while the p-p resolution is calculated based on peak-to-peak noise. the p-p resolution represents the resolution for which there is no code flicker. these numbers are typical and rounded to the nearest lsb. table 8. rms noise (v) vs. gain and output update rate using an internal 1.17 v reference with chop enabled update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 0.81 0.67 0.32 0.2 0.13 0.065 0.04 0.039 8.33 1.18 1.11 0.41 0.25 0.16 0.078 0.058 0.059 16.7 1.96 1.72 0.55 0.36 0.25 0.11 0.088 0.088 33.2 2.99 2.48 0.83 0.48 0.33 0.17 0.13 0.12 62 3.6 3.25 1.03 0.65 0.46 0.2 0.15 0.15 123 5.83 5.01 1.69 0.96 0.67 0.32 0.25 0.26 242 11.22 8.64 2.69 1.9 1.04 0.45 0.35 0.34 470 12.46 10.58 4.58 2 1.27 0.63 0.50 0.49 table 9. effective resolution (bits) vs. gain and ou tput update rate for the ad7794 using an in ternal 1.17 v reference with chop enabled update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 21.5 (19) 20.5 (18) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 20 (17.5) 19 (16.5) 8.33 21 (18.5) 20 (17.5) 20.5 (18) 20 (17.5) 20 (17.5) 20 (17.5) 19 (16.5) 18 (15.5) 16.7 20 (17.5) 19.5 (17) 20 (17.5) 19.5 (17) 19 (16.5) 19.5 (17) 18.5 (16) 17.5 (15) 33.2 19.5 (17) 19 (16.5) 19.5 (17) 19 (16.5) 19 (16.5) 18.5 (16) 18 (15.5) 17 (14.5) 62 19.5 (17) 18.5 (16) 19 (16.5) 19 (16.5) 18.5 (16) 18.5 (16) 18 (15.5) 17 (14.5) 123 18.5 (16) 18 (15.5) 18.5 (16) 18 (15.5) 17.5 (15) 18 (15.5) 17 (14.5) 16 (13.5) 242 17.5 (15) 17 (14.5) 17.5 (15) 17 (14.5) 17 (14.5) 17.5 (15) 16.5 (14) 15.5 (13) 470 17.5 (15) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 17 (14.5) 16 (13.5) 15 (12.5) table 10. effective resolution (bits) vs. gain and ou tput update rate for the ad7795 using an in ternal 1.17 v reference with chop enabled update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 62 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 123 16 (16) 16 (15.5) 16 (16) 16 (15.5) 16 (15) 16 (15.5) 16 (14.5) 16 (13.5) 242 16 (15) 16 (14.5) 16 (15) 16 (14.5) 16 (14.5) 16 (15) 16 (14) 15.5 (13) 470 16 (15) 16 (14.5) 16 (14.5) 16 (14.5) 16 (14.5) 16 (14.5) 16 (13.5) 15 (12.5)
ad7794/ad7795 rev. d | page 15 of 36 chop disabled with chop disabled, the switching time or settling time is reduced by a factor of two. however, periodic offset calibrations may now be required to remove offset and offset drift. when chop is disabled, the amp-cm bit in the mode register should be set to 1. this limits the allowable common-mode voltage that can be used. however, the common-mode rejection degrades if the bit is not set. table 11 shows the rms noise of the ad7794/ad7795 for some of the update rates and gain settings with chop disabled. the numbers given are for the bipolar input range with the internal 1.17 v reference. these numbers are typical and are generated with a differential input voltage of 0 v. table 12 and table 13 show the effective resolution while the output peak-to-peak (p-p) resolution is listed in brackets. it is important to note that the effective resolution is calculated using the rms noise, while the p-p resolution is calculated based on peak-to-peak noise. the p-p resolution represents the resolution for which there is no code flicker. these numbers are typical and rounded to the nearest lsb. table 11. rms noise (v) vs. gain and ou tput update rate using an internal 1. 17 v reference with chop disabled update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 1.22 0.98 0.33 0.18 0.13 0.062 0.053 0.051 8.33 1.74 1.53 0.49 0.29 0.21 0.1 0.079 0.07 16.7 2.64 2.44 0.79 0.48 0.33 0.16 0.13 0.12 33.2 4.55 3.52 1.11 0.66 0.46 0.21 0.17 0.16 62 5.03 4.45 1.47 0.81 0.58 0.27 0.2 0.22 123 8.13 7.24 2.27 1.33 0.96 0.48 0.36 0.37 242 15.12 13.18 3.77 2.09 1.45 0.64 0.5 0.47 470 17.18 14.63 8.86 2.96 1.92 0.89 0.69 0.7 table 12. effective resolution (bits) vs. gain and ou tput update rate for the ad7794 using an in ternal 1.17 v reference with chop disable d update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 21 (18.5) 20 (17.5) 21 (18.5) 20.5 (18) 20 (17.5) 20 (17.5) 19.5 (17) 18.5 (16) 8.33 20.5 (18) 19.5 (17) 20 (17.5) 20 (17.5) 19.5 (17) 19.5 (17) 19 (16.5) 18 (15.5) 16.7 20 (17.5) 19 (16.5) 19.5 (17) 19 (16.5) 19 (16.5) 19 (16.5) 18 (15.5) 17 (14.5) 33.2 19 (16.5) 18.5 (16) 19 (16.5) 19 (16.5) 18.5 (16) 18.5 (16) 17.5 (15) 17 (14.5) 62 19 (16.5) 18 (15.5) 18.5 (16) 18.5 (16) 18 (15.5) 18 (15.5) 17.5 (15) 16.5 (14) 123 18 (15.5) 17.5 (15) 18 (15.5) 17.5 (15) 17 (14.5) 17 (14.5) 16.5 (14) 15.5 (13) 242 17 (14.5) 16.5 (14) 17 (14.5) 17 (14.5) 16.5 ( 14) 17 (14.5) 16 (13.5) 15 (12.5) 470 17 (14.5) 16.5 (14) 16 (13.5) 16.5 (14) 16 (13.5) 16.5 (14) 15.5 (13) 14.5 (12) table 13. effective resolution (bits) vs. gain and ou tput update rate for the ad7795 using an in ternal 1.17 v reference with chop disable d update rate (hz) gain of 1 gain of 2 gain of 4 gain of 8 gain of 16 gain of 32 gain of 64 gain of 128 4.17 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 8.33 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16.7 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15.5) 16 (14.5) 33.2 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (16) 16 (15) 16 (14.5) 62 16 (16) 16 (15.5) 16 (16) 16 (16) 16 (15.5) 16 (15.5) 16 (15) 16 (14) 123 16 (15.5) 16 (15) 16 (15.5) 16 (15) 16 (14.5) 16 (14.5) 16 (14) 15.5 (13) 242 16 (14.5) 16 (14) 16 (14.5) 16 (14.5) 16 (14) 16 (14.5) 16 (13.5) 15 (12.5) 470 16 (14.5) 16 (14) 16 (13.5) 16 (14) 16 (13.5) 16 (14) 15.5 (13) 14.5 (12)
ad7794/ad7795 rev. d | page 16 of 36 typical performance characteristics 8388800 8388450 8388500 8388550 8388600 8388650 8388700 8388750 0 1000 800 600 400 200 04854-006 reading number code read figure 6. typical noise plot for the ad7794 (internal reference, gain = 64, update rate = 16.7 hz, chop enabled) 16 0 2 4 6 8 10 12 14 8388482 8388750 8388720 8388680 8388640 8388600 8388560 8388520 04854-007 occurrence code figure 7. noise distribution histogram for the ad7794 (internal reference, gain = 64, update rate = 16.7 hz, chop enabled) 8388450 8388050 8388100 8388150 8388200 8388250 8388300 8388350 8388400 0 1000 800 600 400 200 04854-008 reading number code read figure 8. typical noise plot for the ad7794 (internal reference, gain = 64, update rate = 16.7 hz, amp-cm = 1, chop disabled) 14 0 2 4 6 8 10 12 8388068 8388396 8388350 8388300 8388250 8388200 8388150 8388100 04854-009 occurrence code figure 9. noise distribution histogram for the ad7794 (internal reference, gain = 64, update rate = 16.7 hz, chop disabled, amp-cm = 1) 20 10 0 ?2.0 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 04854-010 matching (%) (%) figure 10. excitation current matching (210 a) at ambient temperature 90 80 70 60 50 40 30 20 10 0 0 200 400 600 800 1000 04854-011 load capacitance (nf) power-up time (ms) boost = 0 boost = 1 figure 11. bias voltage generator power-up time vs. load capacitance
ad7794/ad7795 rev. d | page 17 of 36 on-chip registers the adc is controlled and configured via a number of on-chip registers that are described in the following sections. in the following descriptions, set implies a logic 1 state and cleared implies a logic 0 state, unless otherwise noted. communications register rs2, rs1, rs0 = 0, 0, 0 the communications register is an 8-bit write-only register. all communications to the part must start with a write operation to the communications register. the data written to the communi- cations register determines whether the next operation is a read or write operation, and to which register this operation takes place. for read or write operations, once the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. this is the default state of the interface and, on power-up or after a reset, the adc is in this default state waiting for a write operation to the communications register. in situations where the interface sequence is lost, a write operation of at least 32 serial clock cycles with din high returns the adc to this default state by resetting the entire part. table 14 outlines the bit designations for the communications register. cr0 through cr7 indicate the bit location, with cr denoting the bits are in the communications register. cr7 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 wen (0) r/ w (0) rs2(0) rs1(0) rs0(0) cread(0) 0(0) 0(0) table 14. communications register bit designations bit no. mnemonic description cr7 wen write enable bit. a 0 must be written to this bit so that the write to the communication s register actually occurs. if a 1 is the first bit written, the part does not clock on to su bsequent bits in the register. it stays at this bit location until a 0 is written to this bit. once a 0 is written to the wen bit, the next seven bits are loaded to the communications register. cr6 r/ w a 0 in this bit location indicates that the next operatio n is a write to a specified register. a 1 in this position indicates that the next operation is a read from the designated register. cr5 to cr3 rs2 to rs0 register address bits. these address bits are used to sele ct which registers of the adc are being selected during this serial interface communication. see table 15 . cr2 cread continuous read of the data register. when this bit is se t to 1 (and the data register is selected), the serial interface is configured so that the data register can be re ad continuously, that is, the contents of the data register are automatically placed on the dout pin when the sclk pulses are applied after the rdy pin goes low to indicate that a conversion is complete. the communications register does not have to be written to for data reads. to enable continuous read mode, the instruction 01011100 must be written to the communications register. to exit the continuous read mode, the instruction 01011000 mu st be written to the communications register while the rdy pin is low. while in continuous read mode, the adc mo nitors activity on the din line so it can receive the instruction to exit continuous read mode. additionally, a reset occurs if 32 consecutive 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is written to the device. cr1 to cr0 0 these bits must be programmed to logic 0 for correct operation. table 15. register selection rs2 rs1 rs0 register register size 0 0 0 communications register during a write operation 8-bit 0 0 0 status register during a read operation 8-bit 0 0 1 mode register 16-bit 0 1 0 configuration register 16-bit 0 1 1 data register 24-bit (ad7794)/16-bit (ad7795) 1 0 0 id register 8-bit 1 0 1 io register 8-bit 1 1 0 offset register 24-bit (ad7794)/16-bit (ad7795) 1 1 1 full-scale register 24-bit (ad7794)/16-bit (ad7795)
ad7794/ad7795 rev. d | page 18 of 36 status register rs2, rs1, rs0 = 0, 0, 0; power-on/reset = 0x80 (ad7795)/0x88 (ad7794) the status register is an 8-bit read-only register. to access the adc status register, the user must write to the communications register, select the next operation to be read, and load bit rs2, bit rs1, and bit rs0 with 0. table 16 outlines the bit designations for the status register. sr0 through sr7 indicate the bit locations, with sr denoting that the bits are in the status register. sr7 denotes the first bit of the data stream. the number in brackets indicates the power- on/reset default status of that bit. sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 rdy (1) err(0) noxref(0) 0(0) 0/1 ch2(0) ch1(0) ch0(0) table 16. status register bit designations bit no. mnemonic description sr7 rdy ready bit for adc. cleared when data is written to the adc data register. the rdy bit is set automatically after the adc data register has been read or a period of time be fore the data register is updated with a new conversion result to indicate to the user not to read the conversion da ta. it is also set when the pa rt is placed in power-down mode. the end of a conversion is also indicated by the dout/ rdy pin. this pin can be used as an alternative to the status register for monitoring the adc for conversion data. sr6 err adc error bit. this bit is written to at the same time as the rdy bit. set to indicate that the result written to the adc data register has been clamped to all 0s or all 1s. error sources include overrange, underrange, or the absence of a reference voltage. cleared by a write operation to start a conversion. sr5 noxref no external reference bit. set to indicate that the selected reference (refin1 or refin2) is at a voltage that is below a specified threshold. when set, conversion results are clamped to all 1s. cleared to indicate that a valid reference is applied to the selected reference pins. the noxref bit is enabled by setting the ref_det bit in the configuration register to 1. the err bit is also set if the voltage applied to the selected reference input is invalid. sr4 0 this bit is automatically cleared . sr3 0/1 this bit is automatically cleared on the ad7795 and is automatically set on the ad7794. sr2 to sr0 ch2 to ch0 these bits indicate which channel is being converted by the adc.
ad7794/ad7795 rev. d | page 19 of 36 mode register rs2, rs1, rs0 = 0, 0, 1; power-on/reset = 0x000a the mode register is a 16-bit read/write register that is used to select the operating mode, the update rate, and the clock source. table 17 outlines the bit designations for the mode register. mr0 through mr15 indicate the bit locations with mr denoting that the bits are in the mode register. mr15 is the first bit of the data stream. the number in parentheses indicates the power-on/reset default status of that bit. any write to the setup register resets the modulator and filter, and sets the rdy bit. mr15 mr14 mr13 mr12 mr11 mr10 mr9 mr8 md2(0) md1(0) md0(0) psw(0) 0(0) 0(0) amp-cm(0) 0(0) mr7 mr6 mr5 mr4 mr3 mr2 mr1 mr0 clk1(0) clk0(0) 0(0) chop-dis(0) fs3(1) fs2(0) fs1(1) fs0(0) table 17. mode register bit designations bit no. mnemonic description mr15 to mr13 md2 to md0 mode select bits. these bits select the operating mode of the ad7794/ad7795 (see table 18 ). mr12 psw power switch control bit. set by user to close the power switch psw to gnd. the power switch can sink up to 30 ma. cleared by user to open the power switch. when the adc is placed in power-down mode, the power switch is opened. mr11 to mr10 0 these bits must be programmed with a logic 0 for correct operation. mr9 amp-cm instrumentation amplifier common-mode bit. this bit is used in conjunction with the chop-dis bit. with chop disabled, the user can operate with a wider range of common-mode voltages when amp-cm is cleared. however, the dc common-mode rejection de grades. with amp-cm set, the span for the common- mode voltage is reduced (see the specifications section). however, the dc common-mode rejection is significantly better. mr8 0 this bit must be programmed with a logic 0 for correct operation. mr7 to mr6 clk1 to clk0 these bits are used to select the clock source fo r the ad7794/ad7795. either the on-chip 64 khz clock can be used or an external clock can be used. the abili ty to use an external clock allows several ad7794/ad7795 devices to be synchronized. also, 50 hz/60 hz reject ion is improved when an accurate external clock drives the ad7794/ad7795. clk1 clk0 adc clock source 0 0 internal 64 khz clock. internal clock is not available at the clk pin. 0 1 internal 64 khz clock. this clock is made available at the clk pin. 1 0 external 64 khz. the external clock can have a 45:55 duty cycle (see the specifications section for the external clock). 1 1 external clock. the external cl ock is divided by 2 within the ad7794/ad7795. mr5 0 this bit must be programmed with a logic 0 for correct operation. mr4 chop-dis this bit is used to enable or disable chop. on power-up or following a reset, chop-dis is cleared so chop is enabled. when chop-dis is set , chop is disabled. this bit is used in conjunction with the amp-cm bit. when chop is disabled, the amp-cm bit should be set . this limits the common-mode voltage that can be used by the adc, but the dc common- mode rejection does not degrade. mr3 to mr0 fs3 to fs0 filter update rate select bits (see table 19 ).
ad7794/ad7795 rev. d | page 20 of 36 table 18. operating modes md2 md1 md0 mode 0 0 0 continuous conversion mode (default). in continuous conversion mode, the adc continuously pe rforms conversions and places the result in the data register. rdy goes low when a conversion is complete. the user can read these conversions by placing the device in continuous read mode whereby the conversions are automatically placed on the dout line when sclk pulses are applied. alternatively, the user can instruct the ad c to output the conversion by writing to the communica- tions register. after power-on, the first conversion is available after a period of 2/f adc when chop is enabled or 1/f adc when chop is disabled. subsequent conversions are available at a frequency of f adc with chop either enabled or disabled. 0 0 1 single conversion mode. when single conversion mode is selected, the adc powers up and performs a single conversion. the oscillator requires 1 ms to power up and settle. the adc then performs the conversion, which takes a time of 2/f adc when chop is enabled, or 1/f adc when chop is disabled. the conversion result is placed in the data register, rdy goes low, and the adc returns to power-down mode. th e conversion remains in the data register and rdy remains active (low) until the data is read or another conversion is performed. 0 1 0 idle mode. in idle mode, the adc filter and modulator are held in a reset state although the modulator clocks are still provided. 0 1 1 power-down mode. in power-down mode, all the ad7794/ad7795 circuitry is powered down including the current sources, power switch, burnout currents, bias voltage generator, and clock circuitry. 1 0 0 internal zero-scale calibration. an internal short is automatically connected to the enable d channel. a calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. rdy goes high when the calibration is initiated and returns low when the calibratio n is complete. the adc is placed in idle mode following a calibration. the measured offset coefficient is placed in the offset register of the selected channel. 1 0 1 internal full-scale calibration. a full-scale input voltage is automatically connected to the selected analog input for this calibration. when the gain equals 1, a calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. for higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled and 2 conversion cycles when chop is disabled. rdy goes high when the calibration is initiated and retur ns low when the calibration is complete. the adc is placed in idle mode following a calibration. the measured full-scale coefficient is placed in the full-scale register of the selected channel. internal full-scale calibrations cannot be performed when the gain equals 128. with th is gain setting, a system full-scale calibration can be performed. a full-scale calibr ation is required each time the gain of a channel is changed to minimize the full-scale error. 1 1 0 system zero-scale calibration. user should connect the system zero-scale input to the ch annel input pins as selected by the ch2 bit, ch1 bit, and ch0 bit. a system offset calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mo de following a calibration. the measured offset coeffi- cient is placed in the offset register of the selected channel. 1 1 1 system full-scale calibration. user should connect the system full-scale input to the channe l input pins as selected by the ch2 bit, ch1 bit, and ch0 bit. a calibration takes two conversion cycles to complete when chop is enabled and one conversion cycle when chop is disabled. rdy goes high when the calibration is initia ted and returns low when the calibration is complete. the adc is placed in idle mode following a cali bration. the measured full-scale coefficient is placed in the full-scale register of the selected channel. a full-scale calibration is required each time the gain of a channel is changed.
ad7794/ad7795 rev. d | page 21 of 36 table 19. update rates available (chop enabled) 1 fs3 fs2 fs1 fs0 f adc (hz) t settle (ms) rejection @ 50 hz/60 hz (internal clock) 0 0 0 0 x x 0 0 0 1 470 4 0 0 1 0 242 8 0 0 1 1 123 16 0 1 0 0 62 32 0 1 0 1 50 40 0 1 1 0 39 48 0 1 1 1 33.2 60 1 0 0 0 19.6 101 90 db (60 hz only) 1 0 0 1 16.7 120 80 db (50 hz only) 1 0 1 0 16.7 120 65 db (50 hz and 60 hz) 1 0 1 1 12.5 160 66 db (50 hz and 60 hz) 1 1 0 0 10 200 69 db (50 hz and 60 hz) 1 1 0 1 8.33 240 70 db (50 hz and 60 hz) 1 1 1 0 6.25 320 72 db (50 hz and 60 hz) 1 1 1 1 4.17 480 74 db (50 hz and 60 hz) 1 with chop disabled, the update rates remain unchanged, but the settling t ime for each update rate is reduced by a factor of 2. the rejection at 50 hz/60 hz for a 16.6 hz update rate degrades to 60 db.
ad7794/ad7795 rev. d | page 22 of 36 configuration register rs2, rs1, rs0 = 0, 1, 0; power-on/reset = 0x0710 the configuration register is a 16-bit read/write register that is used to configure the adc for unipolar or bipolar mode, enable or disable the buffer, enable or disable the burnout currents, select the gain, and select the analog input channel. table 20 outlines the bit designations for the filter register. con0 through con15 indicate the bit locations. con denotes that the bits are in the configuration register. con15 is the first bit of the data stream. the number in parentheses indicates the power-on/reset default status of that bit. con15 con14 con13 con12 con11 con10 con9 con8 vbias1(0) vbias0(0) bo(0) u/ b (0) boost(0) g2(1) g1(1) g0(1) con7 con6 con5 con4 con3 con2 con1 con0 refsel1(0) refsel0(0) ref_det(0) buf(1) ch3(0) ch2(0) ch1(0) ch0(0) table 20. configuration register bit designations bit no. mnemonic description con15 to con14 vbias1 to vbias0 bias voltage generator enable. the negative terminal of the analog inputs can be biased up to av dd /2. these bits are used in conjunction with the boost bit. vbias1 vbias0 bias voltage 0 0 bias voltage generator disabled 0 1 bias voltage generator connected to ain1(?) 1 0 bias voltage generator connected to ain2(?) 1 1 bias voltage generator connected to ain3(?) con13 bo burnout current enable bit. this bit must be progra mmed with a logic 0 for correct operation. when this bit is set to 1 by the user, the 100 na current sources in the signal path are enabled. when bo = 0, the burnout currents are disabled. the burnout currents can be enabled only when the buffer or in-amp is active. con12 u/ b unipolar/bipolar bit. set by user to enable unipolar coding, that is, zero differential input results in 0x000000 output and a full-scale differenti al input results in 0xffffff output. cleared by the user to enable bipolar coding. negative full-scale differenti al input results in an output code of 0x000000, zero differential input results in an output code of 0x800000, and positive full-scale differential input results in an output code of 0xffffff. con11 boost this bit is used in conjunction wi th the vbias1 and vbias0 bits. when set , the current consumed by the bias voltage generator is increased, which reduces its power-up time. con10 to con8 g2 to g0 gain select bits. written by the user to select the adc input range as follows: g2 g1 g0 gain adc input range (2.5 v reference) 0 0 0 1 (in-amp not used) 2.5 v 0 0 1 2 (in-amp not used) 1.25 v 0 1 0 4 625 mv 0 1 1 8 312.5 mv 1 0 0 16 156.2 mv 1 0 1 32 78.125 mv 1 1 0 64 39.06 mv 1 1 1 128 19.53 mv con7 to con6 refsel1/refsel0 reference select bits. the reference source for the adc is selected using these bits. refsel1 refsel0 reference source 0 0 external reference applied between refin1(+) and refin1(?) 0 1 external reference applied between refin2(+) and refin2(?) 1 0 internal 1.17 v reference 1 1 reserved
ad7794/ad7795 rev. d | page 23 of 36 bit no. mnemonic description con5 ref_det enables the reference detect function. when set , the noxref bit in the status register indicates when the external reference being used by the adc is open circuit or less than 0.5 v. when cleared , the reference detect function is disabled. con4 buf configures the adc for buffered or unbuffered mode of operation. if cleared , the adc operates in unbuffered mode, lowering the power consumption of the device. if set , the adc operates in buffered mode, allowing the user to place source impedances on the front end without cont ributing gain errors to the system. for gains of 1 and 2, the buffer can be en abled or disabled. for higher gains, the buffer is automatically enabled. with the buff er disabled, the voltage on the analog input pins can be from 30 mv below gnd to 30 mv above av dd . when the buffer is enabled, it requires some headroom so the voltage on any input pin must be limited to 100 mv within the power supply rails. con3 to con0 ch3 to ch0 channel select bits. written by the user to select the active analog input channel to the adc. ch3 ch2 ch1 ch0 channel calibration pair 0 0 0 0 ain1(+)/ain1(?) 0 0 0 0 1 ain2(+)/ain2(?) 1 0 0 1 0 ain3(+)/ain3(?) 2 0 0 1 1 ain4(+)/ain4(?) 3 0 1 0 0 ain5(+)/ain5(?) 3 0 1 0 1 ain6(+)/ain6(?) 3 0 1 1 0 temp sensor automatically selects the internal 1.17 v reference and sets the gain to 1 0 1 1 1 av dd monitor automatically selects the internal 1.17 v reference and sets the gain to 1/6 1 0 0 0 ain1(?)/ain1(?) 0 1 0 0 1 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved
ad7794/ad7795 rev. d | page 24 of 36 data register rs2, rs1, rs0 = 0, 1, 1; power-on/reset = 0x0000(ad7795), 0x000000 (ad7794) the conversion result from the adc is stored in this data register. this is a read-only register. on completion of a read operation from this register, the rdy bit/pin is set. id register rs2, rs1, rs0 = 1, 0, 0; power-on/reset = 0xxf the identification number for the ad7794/ad7795 is stored in the id register. this is a read-only register. io register rs2, rs1, rs0 = 1, 0, 1; power-on/reset = 0x00 the io register is an 8-bit read/write register that is used to enable the excitation currents and select the value of the excitation currents. table 21 outlines the bit designations for the io register. io0 through io7 indicate the bit locations. io denotes that the bits are in the io register. io7 denotes the first bit of the data stream. the number in brackets indicates the power-on/reset default status of that bit. io7 io6 io5 io4 io3 io2 io1 io0 0(0) ioen(0) io2dat(0) io1dat(0) iexcdir1(0) iexcdir0(0) iexcen1(0) iexcen0(0) table 21. io register bit designations bit no. mnemonic description io7 0 this bit must be programmed with a logic 0 for correct operation. io6 ioen configures pin ain6(+)/p1 and pin ain6(?)/p2 as an alog input pins or digital output pins. when this bit is set , the pins are configured as digital output pin p1 and digital output pin p2. when this bit is cleared , these pins are configured as analog inp ut pin ain6(+) and analog input pin ain6(?). io5 to io4 io2dat/io1dat p2/p1 data. when ioen is set , the data for digital output pin p1 and digital output pin p2 is written to bit io2dat and bit io1dat. io3 to io2 iexcdir1 to iexcdir0 direction of current sources select bits. iexcdir1 iexcdir0 current source direction 0 0 current source iexc1 connected to pin iout1. current source iexc2 connected to pin iout2. 0 1 current source iexc1 connected to pin iout2. current source iexc2 connected to pin iout1. 1 0 both current sources connected to pin iout1. permitted only when the current sources are set to 10 a or 210 a. 1 1 both current sources connected to pin iout2. permitted only when the current sources are set to 10 a or 210 a. io3 to io2 iexcen1 to iexcen0 these bits are used to enable and disable the curr ent sources. they also select the value of the excitation currents. iexcen1 iexcen0 current source value 0 0 excitation currents disabled 0 1 10 a 1 0 210 a 1 1 1 ma
ad7794/ad7795 rev. d | page 25 of 36 offset register rs2, rs1, rs0 = 1, 1, 0; power-on/reset = 0x8000 (ad7795), 0x800000 (ad7794)) the offset register is a 16-bit register on the ad7795 and a 24-bit register on the ad7794. the offset register holds the offset calibration coefficient for the adc and its power-on reset value is 0x8000/0x800000, for the ad7794/ad7795, respectively. the ad7794/ad7795 each have four offset registers. channel ain1 to channel ain3 have dedicated offset registers while the ain4, ain5, and ain6 channels share an offset register. each of these registers is a read/write register. the register is used in conjunction with its associated full-scale register to form a register pair. the power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. the ad7794/ad7795 must be placed in power-down mode or idle mode when writing to the offset register. full-scale register rs2, rs1, rs0 = 1, 1, 1; power-on/reset = 0x5xxx (ad7795), 0x5xxx00 (ad7794) the full-scale register is a 16-bit register on the ad7795 and a 24-bit register on the ad7794. the full-scale register holds the full-scale calibration coefficient for the adc. the ad7794/ ad7795 each have four full-scale registers. the ain1, ain2, and ain3 channels have dedicated full-scale registers, while the ain4, ain5, and ain6 channels share a register. the full-scale registers are read/write registers. however, when writing to the full-scale registers, the adc must be placed in power-down mode or idle mode. these registers are configured on power-on with factory calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. therefore, every device has different default coefficients. the coefficients are different, depending on whether the internal reference or an external reference is selected. the default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or the full-scale register is written to.
ad7794/ad7795 rev. d | page 26 of 36 adc circuit information overview the ad7794/ad7795 are low power adcs that incorporate a - modulator, buffer, reference, in-amp, and on-chip digital filtering, which are intended for the measurement of wide dynamic range, low frequency signals (such as those in pressure transducers), weigh scales, and temperature measurement applications. each part has six differential inputs that can be buffered or unbuffered. the devices operate with an internal 1.17 v refer- ence or by using an external reference. figure 12 shows the basic connections required to operate the parts. the output rate of the ad7794/ad7795 (f adc ) is user pro- grammable. the allowable update rates, along with the corresponding settling times, are listed in table 19 for chop enabled. with chop disabled, the allowable update rates remain unchanged, but the settling time equals 1/f adc . normal mode rejection is the major function of the digital filter. simultaneous 50 hz and 60 hz rejection is optimized when the update rate equals 16.7 hz or less, as notches are placed at both 50 hz and 60 hz with these update rates (see figure 14 ). the ad7794/ad7795 use slightly different filter types, depending on the output update rate, so that the rejection of quantization noise and device noise is optimized. when the update rate is 4.17 hz to 12.5 hz, a sinc3 filter along with an averaging filter is used. when the update rate is 16.7 hz to 39 hz, a modified sinc3 filter is used. this filter gives simultaneous 50 hz/60 hz rejection when the update rate equals 16.7 hz. a sinc4 filter is used when the update rate is 50 hz to 242 hz. finally, an integrate-only filter is used when the update rate equals 470 hz. figure 13 to figure 16 show the frequency response of the different filter types for some of the update rates when chop is enabled. in this mode, the settling time equals twice the update rate. figure 17 to figure 20 show the filter response with chop disabled. 04854-012 dout/rd y din sclk cs dv dd serial interface and logic control - adc ad7794/ad7795 ain1(+) refin1(+) ain1(?) ain2(+) ain2(?) ain3(+) ain3(?) refin2(+) iout1 refin1(?) in-amp v dd gnd mux psw gnd internal clock clk gnd av dd v dd in+ in? out? out+ in+ in? out? out+ r cm v dd refin2(?) buf figure 12. basic connection diagram
ad7794/ad7795 rev. d | page 27 of 36 100 80 60 40 20 04854-017 frequency (hz) (db) 0 ?20 ?40 ?60 ?80 ?100 01 2 0 figure 13. filter response with update rate = 4.17 hz (chop enabled) 0 ?20 ?40 ?60 ?80 ?100 02 0 0 0 ?10 ?20 ?30 ?40 ?50 ?60 0 10000 9000 8000 7000 6000 5000 4000 3000 2000 1000 04854-020 frequency (hz) (db) figure 16. filter response with up date rate = 470 hz (chop enabled) 0 ?100 ?80 ?60 ?40 ?20 01 2 0 100 80 60 40 20 04854-021 frequency (hz) (db) figure 17. filter response with update rate = 4.17 hz (chop disabled) 0 ?100 ?80 ?60 ?40 ?20 02 100 120 140 160 180 80 604020 04854-022 frequency (hz) (db) 180 160140120 10080 604020 04854-018 frequency (hz) (db) figure 14. filter response with update rate = 16.7 hz (chop enabled) 0 ?20 ?40 ?60 ?80 ?100 0 3000 2500 2000 1500 1000 500 04854-019 frequency (hz) (db) figure 15. filter response with update rate = 242 hz (chop enabled) 0 0 figure 18. filter response with update rate = 16.7 hz (chop disabled)
ad7794/ad7795 rev. d | page 28 of 36 0 ?20 ?40 ?60 ?80 ?100 0 3000 2500 2000 1500 1000 500 04854-023 frequency (hz) (db) figure 19. filter response at 242 hz update rate (chop disabled) 0 ?60 ?50 ?40 ?30 ?10 ?20 0 10000 5000 6000 7000 8000 9000 4000 3000 2000 1000 04854-024 frequency (hz) (db) figure 20. filter response at 470 hz update rate (chop disabled) digital interface as previously outlined in the on-chip registers section, the programmable functions of the ad7794/ad7795 are controlled using a set of on-chip registers. data is written to these registers via the serial interface. read access to the on-chip registers is also provided by this interface. all communications with the parts must start with a write to the communications register. after power-on or reset, each device expects a write to its communications register. the data written to this register determines whether the next operation is a read operation or a write operation, and determines to which register this read or write operation occurs. therefore, write access to any of the other registers on the parts begins with a write operation to the communications register, followed by a write to the selected register. a read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. the serial interface of the ad7794/ad7795 consists of four signals: cs , din, sclk, and dout/ rdy . the din line is used to transfer data into the on-chip registers, while dout/ rdy is used for accessing data from the on-chip registers. sclk is the serial clock input for the devices, and all data transfers (either on din or dout/ rdy ) occur with respect to the sclk signal. the dout/ rdy pin also operates as a data ready signal; the line goes low when a new data-word is available in the output register. it is reset high when a read operation from the data register is complete. it also goes high prior to the updating of the data register to indicate when not to read from the device, to ensure that a data read is not attempted while the register is being updated. cs is used to select a device. it can be used to decode the ad7794/ad7795 in systems where several components are connected to the serial bus. figure 3 and figure 4 show timing diagrams for interfacing to the ad7794/ad7795 with cs , which is being used to decode the parts. figure 3 shows the timing for a read operation from the output shift register of the ad7794/ad7795, while figure 4 shows the timing for a write operation to the input shift register. it is possible to read the same word from the data register several times, even though the dout/ rdy line returns high after the first read operation. however, care must be taken to ensure that the read operations have been completed before the next output update occurs. in continuous read mode, the data register can be read only once. the serial interface can operate in 3-wire mode by tying cs low. in this case, the sclk, din, and dout/ rdy lines are used to communicate with the ad7794/ad7795. the end of the conversion can be monitored using the rdy bit in the status register. this scheme is suitable for interfacing to micro- controllers. if cs is required as a decoding signal, it can be generated from a port pin. for microcontroller interfaces, it is recommended that sclk idle high between data transfers. the ad7794/ad7795 can be operated with cs being used as a frame synchronization signal. this scheme is useful for dsp interfaces. in this case, the first bit (msb) is effectively clocked out by cs , because cs normally occurs after the falling edge of sclk in dsps. the sclk can continue to run between data transfers, provided the timing numbers are obeyed. the serial interface can be reset by writing a series of 1s on the din input. if a logic 1 is written to the ad7794/ad7795 line for at least 32 serial clock cycles, the serial interface is reset. this ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. reset returns the interface to the state in which it is expecting a write to the communications register. this operation resets the contents of all registers to their power-on values. following a reset, the user should allow a period of 500 s before addressing the serial interface. the ad7794/ad7795 can be config ured to continuously convert or perform a single conversion (see figure 21 through figure 23 ).
ad7794/ad7795 rev. d | page 29 of 36 04854-014 data sclk dout/rdy cs 0x58 din 0x08 0x200a figure 21. single conversion 0 4854-015 din sclk dout/rdy cs 0x58 0x58 data data figure 22. continuous conversion 0 4854-016 din sclk dout/rdy cs 0x5c data data data figure 23. continuous read
ad7794/ad7795 rev. d | page 30 of 36 single conversion mode in single conversion mode, the ad7794/ad7795 are placed in shutdown mode between conversions. when a single conversion is initiated by setting md2 to 0, md1 to 0, and md0 to 1 in the mode register, the ad7794/ad7795 power up, perform a single conversion, and then return to shutdown mode. the on-chip oscillator requires 1 ms to power up. a conversion requires a time period of 2 t adc . dout/ rdy goes low to indicate the completion of a conversion. when the data- word has been read from the data register, dout/ rdy goes high. if cs is low, dout/ rdy remains high until another conversion is initiated and completed. the data register can be read several times, if required, even when dout/ rdy has gone high. continuous conversion mode this is the default power-up mode. the ad7794/ad7795 continuously convert with the rdy pin in the status register going low each time a conversion is complete. if cs is low, the dout/ rdy line also goes low when a conversion is complete. to read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. the digital conversion is placed on the dout/ rdy pin as soon as sclk pulses are applied to the adc. dout/ rdy returns high when the conversion is read. the user can read this register additional times, if required. however, the user must ensure that the data register is not being accessed at the completion of the next conversion, or else the new conversion word is lost. continuous read rather than write to the communications register each time a conversion is complete to access the data, the ad7794/ad7795 can be configured so that the conversions are placed on the dout/ rdy line automatically. by writing 01011100 to the communications register, the user need only apply the appropriate number of sclk cycles to the adc. the 24-bit word is automatically placed on the dout/ rdy line when a conversion is complete. the adc should be configured for continuous conversion mode. when dout/ rdy goes low to indicate the end of a conversion, sufficient sclk cycles must be applied to the adc, and the data conversion is placed on the dout/ rdy line. when the conversion is read, dout/ rdy returns high until the next conversion is available. in this mode, the data can be read only once. also, the user must ensure that the data-word is read before the next conversion is complete. if the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the ad7794/ad7795 to read the word, the serial output register is reset when the next conversion is complete. the new conversion is then placed in the output serial register. to exit the continuous read mode, the instruction 01011000 must be written to the communications register while the rdy pin is low. while in the continuous read mode, the adc monitors activity on the din line so that it can receive the instruction to exit the continuous read mode. additionally, a reset occurs if 32 consecutive 1s are seen on din. therefore, din should be held low in continuous read mode until an instruction is to be written to the device.
ad7794/ad7795 rev. d | page 31 of 36 circuit description analog input channel the ad7794/ad7795 have six differential analog input channels. these are connected to the on-chip buffer amplifier when the devices are operated in buffered mode. when in unbuffered mode, the channels connect directly to the modulator. in buffered mode (the buf bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gages or resistance temperature detectors (rtds). when buf = 0, the parts operate in unbuffered mode. this results in a higher analog input current. note that this unbuffered input path provides a dynamic load to the driving source. therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the adc input. table 22 shows the allowable external resistance/capacitance values for unbuffered mode so that no gain error at the 20-bit level is introduced. table 22. external r-c combination for 20-bit no gain error capacitance (pf) resistance () 50 9 k 100 6 k 500 1.5 k 1000 900 5000 200 the ad7794/ad7795 can be operated in unbuffered mode only when the gain equals 1 or 2. at higher gains, the buffer is automatically enabled. the absolute input voltage range in buffered mode is restricted to a range between gnd + 100 mv and av dd ? 100 mv. when the gain is set to 4 or higher, the in-amp is enabled. the absolute input voltage range when the in- amp is active is restricted to a range between gnd + 300 mv and av dd ? 1.1 v. care must be taken in setting up the common- mode voltage so that these limits are not exceeded. otherwise, there is degradation in linearity and noise performance. the absolute input voltage in unbuffered mode includes the range between gnd ? 30 mv and av dd + 30 mv as a result of being unbuffered. the negative absolute input voltage limit does allow the possibility of monitoring small, true bipolar signals with respect to gnd. instrumentation amplifier amplifying the analog input signal by a gain of 1 or 2 is performed digitally within the ad7794/ad7795. however, when the gain equals 4 or higher, the output from the buffer is applied to the input of the on-chip instrumentation amplifier. this low noise in-amp means that signals of small amplitude can be gained within the ad7794/ad7795 while still maintaining excellent noise performance. for example, when the gain is set to 64, the rms noise is 40 nv typically, which is equivalent to 21 bits effective resolution or 18.5 bits peak-to- peak resolution. each ad7794/ad7795 can be programmed to have a gain of 1, 2, 4, 8, 16, 32, 64, and 128 using bit g2 to bit g0 in the configuration register. therefore, with an external 2.5 v reference, the unipolar ranges are from 0 mv to 20 mv to 0 v to 2.5 v and the bipolar ranges are from 20 mv to 2.5 v. when the in-amp is active (gain 4), the common-mode voltage ((ain(+) + ain(?))/2) must be greater than or equal to 0.5 v when chop is enabled. with chop disabled, and with the amp-cm bit set to 1 to prevent degradation in the common- mode rejection, the allowable common-mode voltage is limited to between 0.2 + (gain/2 ( ain(+) ? ain(?) )) and av dd ? 0.2 ? (gain / 2 (ain(+) ? ain(?) )) if the ad7794/ad7795 are operated with an external reference that has a value equal to av dd , for correct operation, the analog input signal must be limited to 90% of v ref /gain when the in- amp is active. bipolar/unipolar configuration the analog input to the ad7794/ad7795 can accept either unipolar or bipolar input voltage ranges. a bipolar input range does not imply that the parts can tolerate negative voltages with respect to system gnd. unipolar and bipolar signals on the ain(+) input are referenced to the voltage on the ain(?) input. for example, if ain(?) is 2.5 v and the adc is configured for unipolar mode with a gain of 1, the input voltage range on the ain(+) pin is 2.5 v to 5 v. if the adc is configured for bipolar mode, the analog input range on the ain(+) input is 0 v to 5 v. the bipolar/unipolar option is chosen by programming the u/ b bit in the configuration register.
ad7794/ad7795 rev. d | page 32 of 36 data output coding when the adc is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a miscalled voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. the output code for any analog input voltage can be represented as code = (2 n ain gain )/ v ref when the adc is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. the output code for any analog input voltage can be represented as code = 2 n C 1 [( ain gain / v ref ) + 1] where: ain is the analog input voltage. gain is the in-amp setting (1 to 128). n = 24. burnout currents the ad7794/ad7795 contain two 100 na constant current generators, one sourcing current from av dd to ain(+), and one sinking current from ain(?) to gnd. the currents are switched to the selected analog input pair. both currents are either on or off, depending on the burnout current enable (bo) bit in the configuration register. these currents can be used to verify that an external transducer is still operational before attempting to take measurements on that channel. once the burnout currents are turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. if the resulting voltage measured is full scale, the user needs to verify why this is the case. a full-scale reading could mean that the front-end sensor is open circuit. it could also mean that the front-end sensor is overloaded and is justified in outputting full scale, or that the reference may be absent and the noxref bit is set, thus clamping the data to all 1s. when reading all 1s from the output, the user needs to check these three cases before making a judgment. if the voltage measured is 0 v, it may indicate that the transducer has short circuited. for normal operation, these burnout currents are turned off by writing a 0 to the bo bit in the configuration register. the current sources work over the normal absolute input voltage range specifications with buffers on. excitation currents the ad7794/ad7795 also contain two matched, software configurable, constant current sources that can be programmed to equal 10 a, 210 a, or 1 ma. both source currents from av dd are directed to either the iout1 or iout2 pin of the device. these current sources are controlled via bits in the io register. the configuration bits enable the current sources and direct the current sources to iout1 or iout2, along with selecting the value of the current. these current sources can be used to excite external resistive bridge or rtd sensors. bias voltage generator a bias voltage generator is included on the ad7794/ad7795. it biases the negative terminal of the selected input channel to av dd /2. this function is available on inputs ain1(?) to ain3(?). it is useful in thermocouple applications, as the voltage generated by the thermocouple must be biased about some dc voltage if the gain is greater than 2. this is necessary because the instrumentation amplifier requires headroom. if there is no headroom, signals close to gnd or av dd do not convert accurately. the bias voltage generator is controlled using the vbias1 and vbias0 bits in conjunction with the boost bit in the configuration register. the power-up time of the bias voltage generator is dependent on the load capacitance. to accommodate higher load capacitances, each ad7794/ad7795 has a boost bit. when this bit is set to 1, the current consumed by the bias voltage generator is increased so that power-up time is reduced considerably. figure 11 shows the power-up times when boost equals 0 and boost equals 1 for different load capacitances. the current consumption of the ad7794/ad7795 increases by 40 a when the bias voltage generator is enabled, and boost equals 0. with the boost function enabled, the current consumption increases by 250 a. reference the ad7794/ad7795 have embedded 1.17 v references. these references can be used to supply the adc or external references can be applied. the embedded references are low noise, low drift references with 4 ppm/c drift typically. for external references, the adc has a fully differential input capability for the channel. in addition, the user has the option of selecting one of two external reference options (refin1 or refin2). the reference source for the ad7794/ad7795 is selected using the refsel1 and refsel0 bits in the configuration register. when the internal reference is selected, it is internally connected to the modulator (it is not available on the refin pins). the common-mode range for these differential inputs is from gnd to av dd . the reference input is unbuffered; therefore, excessive r-c source impedances introduce gain errors. the reference voltage refin (refin(+) ? refin(?)) is 2.5 v nominal, but the ad7794/ad7795 are functional with reference voltages from 0.1 v to av dd . in applications where the excitation (voltage or current) for the transducer on the analog
ad7794/ad7795 rev. d | page 33 of 36 input also drives the reference voltage for the parts, the effect of the low frequency noise in the excitation source is removed, because the application is ratiometric. if the ad7794/ad7795 are used in nonratiometric applications, a low noise reference should be used. recommended 2.5 v reference voltage sources for the ad7794/ad7795 include the adr381 and adr391 , which are low noise, low power references. also, note that the reference inputs provide a high impedance, dynamic load. because the input impedance of each reference input is dynamic, resis- tor/capacitor combinations on these inputs can cause dc gain errors, depending on the output impedance of the source driving the reference inputs. reference voltage sources (for example, the adr391 ) typically have low output impedances and are, therefore, tolerant to having decoupling capacitors on refin(+) without introducing gain errors in the system. deriving the reference input voltage across an external resistor means that the reference input sees a significant external source impedance. external decoupling on the refin pins is not recommended in this type of circuit configuration. reference detect the ad7794/ad7795 include on-chip circuitry to detect if they have a valid reference for conversions or calibrations when the user selects an external reference as the reference source. this feature is enabled when the ref_det bit in the configuration register is set to 1. if the voltage between the selected refin(+) and refin(C) pins goes below 0.3 v, or either the refin(+) or refin(C) inputs are open circuit, the ad7794/ad7795 detect that they no longer have valid references. in this case, the noxref bit of the status register is set to 1. if the ad7794/ ad7795 are performing normal conversions and the noxref bit becomes active, the conversion results revert to all 1s. therefore, it is not necessary to continuously monitor the status of the noxref bit when performing conversions. it is only necessary to verify its status if the conversion result read from the adc data register is all 1s. if the ad7794/ad7795 are performing either offset or full-scale calibrations and the noxref bit becomes active, the updating of the respective calibration registers is inhibited to avoid loading incorrect coefficients to these registers, and the err bit in the status register is set. if the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the err bit should be checked at the end of the calibration cycle. reset the circuitry and serial interface of the ad7794/ad7795 can be reset by writing 32 consecutive 1s to the device. this resets the logic, the digital filter, and the analog modulator, and all on- chip registers are reset to their default values. a reset is automatically performed on power-up. when a reset is initiated, the user must allow a period of 500 s before accessing any of the on-chip registers. a reset is useful if the serial interface becomes asynchronous due to noise on the sclk line. av dd monitor along with converting external voltages, the adc can be used to monitor the voltage on the av dd pin. when bit ch2 to bit ch0 equals 1, the voltage on the av dd pin is internally attenuated by 6, and the resulting voltage is applied to the - modulator using an internal 1.17 v reference for analog- to-digital conversion. this is useful because variations in the power supply voltage can be monitored. calibration the ad7794/ad7795 provide four calibration modes that can be programmed via the mode bits in the mode register. these are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration, which effectively reduce the offset error and full-scale error to the order of the noise. after each conversion, the adc conversion result is scaled using the adc calibration registers before being written to the data register. the offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient. to start a calibration, write the relevant value to the md2 to md0 bits in the mode register. after the calibration is completed, the contents of the corresponding calibration registers are updated, the rdy bit in the status register is set, the dout/ rdy pin goes low (if cs is low), and the ad7794/ad7795 revert to idle mode. during an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the adc input pins. a system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the adc pins before initiating the calibration mode. in this way, external adc errors are removed. from an operational point of view, a calibration should be treated like another adc conversion. a zero-scale calibration, if required, should always be performed before a full-scale calibration. system software should monitor the rdy bit in the status register or the dout/ rdy pin to determine the end of calibration via a polling sequence or an interrupt-driven routine. with chop enabled, both an internal offset calibration and a system offset calibration take two conversion cycles. with chop enabled, an internal offset calibration is not needed because the adc itself removes the offset continuously. with chop disabled, an internal offset calibration or system offset calibration takes one conversion cycle to complete. internal offset calibrations are required with chop disabled and should occur before the full-scale calibration. to perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. when the gain equals 1, a calibration takes two conversion cycles to complete when chop is enabled and
ad7794/ad7795 rev. d | page 34 of 36 one conversion cycle when chop is disabled. for higher gains, four conversion cycles are required to perform the full-scale calibration when chop is enabled, and two conversion cycles when chop is disabled. dout/ rdy goes high when the calibration is initiated and returns low when the calibration is complete. the adc is placed in idle mode following a cali- bration. the measured full-scale coefficient is placed in the full- scale register of the selected channel. internal full-scale calibrations cannot be performed when the gain equals 128. with this gain setting, a system full-scale calibration can be performed. a full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. an internal full-scale calibration can be performed at specified update rates only. for gains of 1, 2, and 4, an internal full-scale calibration can be performed at any update rate. however, for higher gains, internal full-scale calibrations can be performed only when the update rate is less than or equal to 16.7 hz, 33.3 hz, and 50 hz. however, the full-scale error does not vary with update rate, so a calibration at one update is valid for all update rates (assuming the gain or reference source is not changed). a system full-scale calibration takes two conversion cycles to complete, irrespective of the gain setting when chop is enabled and one conversion cycle when chop is disabled. a system full- scale calibration can be performed at all gains and all update rates. with chop disabled, the offset calibration (internal or system offset) should be performed before the system full-scale calibration is initiated. grounding and layout because the analog inputs and reference inputs of the adc are differential, most of the voltages in the analog modulator are common-mode voltages. the excellent common-mode rejection of the part removes common-mode noise on these inputs. the digital filter provides rejection of broadband noise on the power supply, except at integer multiples of the modulator sampling frequency. the digital filter also removes noise from the analog and reference inputs, provided that these noise sources do not saturate the analog modulator. as a result, the ad7794/ad7795 are more immune to noise interference than conventional high resolution converters. however, because the resolution of the ad7794/ad7795 is so high, and the noise levels from the ad7794/ad7795 are so low, care must be taken with regard to grounding and layout. the printed circuit board that houses the ad7794/ad7795 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. a minimum etch technique is generally best for ground planes because it gives the best shielding. it is recommended that th e gnd pin of the ad7794/ad7795 be tied to the agnd plane of the system. in any layout, it is important that the user keep in mind the flow of currents in the system, ensuring that the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. avoid forcing digital currents to flow through the agnd sections of the layout. the ground plane of the ad7794/ad7795 should be allowed to run under the ad7794/ad7795 to prevent noise coupling. the power supply lines to the ad7794/ad7795 should use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. in addition, clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is the best, but it is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is important when using high resolution adcs. av dd should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to gnd. dv dd should be decoupled with 10 f tantalum in parallel with 0.1 f capacitors to the systems dgnd plane, with the systems agnd to dgnd connection being close to the ad7794/ad7795. to achieve the best from these decoupling components, they should be placed as close as possible to the device, ideally right up against the device. all logic chips should be decoupled with 0.1 f ceramic capacitors to dgnd.
ad7794/ad7795 rev. d | page 35 of 36 applications information the ad7794/ad7795 offer low cost, high resolution analog-to- digital functions. because the analog-to-digital function is provided by a - architecture, it makes the parts more immune to noisy environments, making them ideal for use in sensor measurement, and industrial and process control applications. flowmeter figure 24 shows the ad7794/ad7795 being used in a flowmeter application that consists of two pressure transducers, with the rate of flow being equal to the pressure difference. the pressure transducers shown are the bp01 from sensym. the pressure transducers are arranged in a bridge network and give a differential output voltage between its out+ and outC terminals. with rated full-scale pressure (in this case 300 mmhg) on the transducer, the differential output voltage is 3 mv/v of the input voltage (that is, the voltage between the in(+) and in(C) terminals). assuming a 5 v excitation voltage, the full-scale output range from the transducer is 15 mv. the excitation voltage for the bridge can be used to directly provide the reference for the adc, as the reference input range includes the supply voltage. a second advantage of using th e ad7794/ad7795 in transducer- based applications is that the low-side power switch can be fully utilized in low power applications. the low-side power switch is connected in series with the cold side of the bridges. in normal operation, the switch is closed and measurements can be taken. in applications where power is of concern, the ad7794/ad7795 can be placed in standby mode, thus significantly reducing the power consumed in the application. in addition, the low-side power switch can be opened while in standby mode, thus avoiding unnecessary power consumption by the front-end transducers. when the parts are taken out of standby mode, and the low-side power switch is closed, the user should ensure that the front-end circuitry is fully settled before attempting a read from the ad7794/ad7795. in the diagram, temperature compensation is performed using a thermistor. the on-chip excitation current supplies the thermistor. in addition, the reference voltage for the temperature measurement is derived from a precision resistor in series with the thermistor. this allows a ratiometric measurement so that variation of the excitation current has no effect on the measurement (it is the ratio of the precision reference resistance to the thermistor resistance that is measured). 04854-025 dout/rd y din sclk cs dv dd serial interface and logic control - adc ad7794/ad7795 ain1(+) refin1(+) ain1(?) ain2(+) ain2(?) ain3(+) ain3(?) refin2(+) iout1 refin1(?) in-amp v dd gnd mux psw gnd internal clock clk gnd av dd v dd in+ in? out? out+ in+ in? out? out+ r cm v dd refin2(?) buf figure 24. typical application (flowmeter)
ad7794/ad7795 rev. d | page 36 of 36 outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 25. 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters ordering guide model temperature range package description package option ad7794bru C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad7794bru-reel C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad7794bruz 1 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad7794bruz-reel 1 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 AD7794CRUZ 1 C40c to +125c 24-lead thin shrink small outline package [tssop] ru-24 AD7794CRUZ-reel 1 C40c to +125c 24-lead thin shrink small outline package [tssop] ru-24 ad7795bruz 1 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 ad7795bruz-reel 1 C40c to +105c 24-lead thin shrink small outline package [tssop] ru-24 eval-ad7794eb evaluation board eval-ad7795eb evaluation board 1 z = rohs compliant part. ?2004-2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04854-0-3/07(d)

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